Authors: Rand B. Mohammed1 & Roelof van Silfhout2
1Mechatronics Engineering Department, Ishik University, Erbil, Iraq
2School of Electrical and Electronic Engineering, University of Manchester, United Kingdom
Abstract: With the all transceiver systems the transmission speed is the most critical factor. The main objective of this paper is to design a new reference model for the multi-link system that is used to carry images in a real-time system, with a high resolution at high transceiver speeds, between two applications over physical media. The new system, called Transceiver System based on Rapid-I/O protocol (TRIO), for both transmitter and receiver, based on eight parallel devices was placed at the bottom of the system architecture, at both transmitter and receiver. The transceiver system is designed as scalable system in which the system data rate increased when multiple lines connected in parallel are used to carry data between the transmitter and the receiver instead of using a single line. By transmitting the same packet of data, once over a single transceiver system and then over eight transceiver systems, ideally an eightfold improvement in bit-rate is expected. The TRIO is implemented on a field programmable gate array (FPGA) and a Terasic DE4 board will be used as the main platform for implementing and testing the embedded system, while Quartus-II software and tools are used to design and debug the embedded hardware system.
Keywords: Rapid-IO Protocol, High Transceiver Speed, Parallel Transceiver Systems, Embedded System, FPGA
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